1. Field of the Invention
The invention generally relates to integrated circuit design and more specifically relates to electronic circuit structures, and associated systems and methods, for an SRAM process monitor cell in integrated circuit design.
2. Discussion of Related Art
In the design of electronic circuits and systems it is well-known that the testing at the point of manufacture can help in reducing subsequent failures of such circuits and systems. Such early testing in the fabrication of electronic circuits and systems is often more cost-effective than later discovery of failures caused by the manufacturing process after products are created and utilized based on the flawed circuits and systems.
Historically, electronic circuits and systems were comprised of discrete electronic components mounted on the surface of printed circuit boards. Metal traces applied to the surfaces of such printed circuit boards provided interconnection of signals between the various discrete electronic components. Testing of such historical electronic circuits and systems following fabrication thereof was a simpler process. Probes could be physically applied to the various interconnected signal pathways to verify operation of each circuit as within specified parameters. Such probing could be done automatically using various robotic and automation devices and processes or could be preformed manually.
Later in the evolution of electronic circuits and systems, small-scale integrated circuits (xe2x80x9cSSIxe2x80x9d) arose in which a small number of formerly discrete components were integrated into a single integrated circuit package. Although such SSI integrated circuits exposed a number of input and output signal paths through pins of the integrated circuit, various internal signal pathways within the integrated circuit were hidden from view. Such SSI devices led to some difficulties in testing electronic circuits and systems following fabrication because certain signal pathways were hidden within the integrated circuit packages of such small-scale integration devices. However, in view of the low degree of integration, relatively few such signal paths were rendered inaccessible for purposes of testing. Standard testing techniques as noted above were still applicable and useful even with such small-scale integration in the electronic circuit and system designs.
As the electronics industry further involved, the degree of such integration progressed to the point where present complex integrated circuit packages may include millions or even tens of millions of electronic circuits and interconnection pathways. Such a high degree of integration (sometimes referred to as very large-scale integration or VLSI) gives rise to significant difficulties in testing such integrated circuits post fabrication. A very large number of internal signal paths and devices are inaccessible external to the integrated circuit package and therefore cannot be effectively probed manually or automatically to evaluate the performance of an integrated circuit relative to specified parameters. Further exacerbating the problem of such circuit testing is the fact that the high degree of integration coupled with very high signaling speeds (i.e. very high clock rates) in modem integrated circuits requires extremely small tolerances in the integrated circuit manufacturing process. Conductive and dielectric material layers are deposited and etched in a substrate with sub-micron dimensions within the integrated circuit die. Manufacturing tolerances for such microscopic device structures are extremely tight. Small variations in the fabrication process can rendered devices unusable as outside specified parameters for proper functionality. Detecting such failures and variations in the fabrication process is a continuing problem in the design and manufacture of highly integrated circuits.
One common technique generally utilized in the design and fabrication of integrated circuits is to incorporate special circuitry intended solely for monitoring the quality of the fabrication process. Such special circuitry is often referred to as xe2x80x9cprocess monitorxe2x80x9d circuits or cells. As used herein, circuit and cell are used interchangeably. The term xe2x80x9ccellxe2x80x9d Is often used in integrated circuit design where libraries of xe2x80x9cstandard cellsxe2x80x9d (pre existing circuit architectures).are selected and used to generate a new custom integrated circuit design. Process monitor circuits are Included in the integrated circuit design by the design engineer and may be probed in post fabrication test procedures to determine if the fabrication process resulted in manufactured process monitor cells that function in accordance with desired specifications. Operation of the processes monitor cells provides a statistical basis for determining the quality of the fabrication process for the entire integrated circuit.
In general, process monitor circuits and cells consist of a number of standard gates and interconnecting signal pathways to allow for post fabrication testing of standard logic gate structures and interconnecting signal pathways within an integrated circuit design. Such process monitor cells serve as a statistical indicator of the quality of the fabrication process that produced the corresponding integrated circuit. If the process monitor cell operates in accordance with specified parameters as determined by post fabrication testing, the entire integrated circuit is presumed to have been manufactured with similar fabrication quality and therefore within specified parameters. If, conversely, the process monitor cell fails to operate within desired specified parameters, the corresponding integrated circuit may be presumed to include similar fabrication flaws and therefore may be discarded or downgraded prior to shipment or inclusion within other systems.
Often such process monitor circuits and cells are designed into an integrated circuit as xe2x80x9cscribe line devices.xe2x80x9d Typically, modem integrated circuits are manufactured as a plurality of identical structures on a large substrate wafer. A scribe line is a boundary area of between adjacent integrated circuits on such a substrate wafer. The plurality of integrated circuits on a wafer are separated by scribe lines where the wafer will eventually be sliced to separate the individual integrated circuits. Scribe line devices are therefore electronic devices or signal paths designed into such scribe line areas separating the integrated circuits such that they may be utilized in post fabrication testing to test Integrated circuit quality and then may be discarded when the wafer is cut along the scribe lines to separate individual integrated circuits. Such scribe line devices allow designers to implement process monitor cells without utilizing valuable area within the intended integrated circuit design.
One significant problem in the use of scribe line devices for process monitor testing is that the scribe line devices may only be utilized while the entire wafer is intact. The scribe line devices are destroyed (or rendered otherwise inoperable) when the wafer is cut to separate individual integrated circuits. Hence, scribe line devices are incapable of testing individual integrated circuits once they have been cut from the wafer and packaged as a production component.
It is a particular problem to test the quality of a fabrication process for static RAM (xe2x80x9cSRAMxe2x80x9d) devices. SRAM devices in integrated circuits are particularly small devices operating with very tight timing tolerances. The transistors and signal pathways in such SRAM devices are therefore more susceptible to fabrication process variations that affect the transistors size and interconnecting traces. For example, the impact of process variations on the current source/sink properties of such small transistors is proportionally greater than the Impact of the same process variations on larger devices of the integrated circuit. Electronic circuit designers therefore take great care in the design of SRAM components within an integrated circuit.
Because of these proportionately larger effects on small devices, existing process monitor cell architectures are inadequate for testing the fabrication process quality as it relates to such intricate SRAM structures. Standard process monitor circuits, as noted above, presently generally consist of standard logic gate and interconnect pathways to verify the quality of the fabrication process with respect to such devices. However, because of the enhanced sensitivity of SRAM devices to fabrication process variations, such existing process monitor cell structures are inadequate.
One current approach for evaluating fabrication process quality with respect to SRAM devices simply rely on inadequate evaluation by existing process monitor cell structures. As noted, such reliance on existing process monitor cells for testing fabrication quality as it relates to SRAM structures provides inadequate testing of SRAM structures within an integrated circuit. Another approach adds scribe line devices to enable external probing of current sink/source capabilities of pass gate transistors of SRAM memory cell structures within the integrated circuit design. Such testing requires external probing to determine current draw through the SRAM transistors as exposed through the scribe line devices. Further, as noted above, scribe line devices are destroyed when the wafer is sliced into individual integrated circuit devices and hence testing may only be performed on a full wafer of circuits rather than individual packaged integrated circuits.
It is therefore evident from the above discussion that a need exists for improved process monitor circuits and techniques specifically adapted for evaluating fabrication process quality with respect to SRAM structures of an integrated circuit.
The present intervention solves the above and other problems, thereby advancing the state of the useful arts, by providing a new process monitor circuit structure and technique specifically adapted to evaluate fabrication process quality as regards to SRAM structures. More specifically, the improved process monitor circuit structure utilizes SRAM cell structures added to a circuit design to evaluate parametric measurements of the SRAM fabrication process. In one aspect, the invention measures the current sink performance of SRAM transistors in the SRAM cells of the process monitor circuit. In another aspect of the invention, the process monitor circuit measures transistor performance and propagation delays in SRAM cell components of the process monitor circuit.